As the power of computing systems and density of memory storage devices continues to increase, a limiting factor on the performance of a computing system is the data bandwidth (rate of data transfer) between a computing device and an associated memory. One way to increase the bandwidth of a data bus (a collection of lines carrying data signals) is to improve the efficiency of the bus, for example, by minimizing the amount of time the bus is idle. Synchronous systems provide one way to increase bus efficiency.
Synchronous systems include a number of devices that operate in synchronism with a system clock. For example, a synchronous memory device can be configured to provide output data a set number of clock cycles following the application of an address. Thus, devices that read data from such a memory (such as a microprocessor, or the like) do not have to monopolize the data bus following a read command, as they will know exactly when the data will be available. For even more efficient transfer of data, a synchronous memory devices can include a burst mode. In a burst mode, data can be read from, or written to the device, on consecutive memory cycles.
Because synchronous devices usually utilize the system clock for internal timing, a limitation on synchronous device operation can occur due to propagation delay of the clock signal through the device. For example, a synchronous memory device could buffer a system clock signal to generate an internal clock signal. Input/output (I/O) circuits, which control the input and output of data into the memory device, are controlled by the internal clock signal. Due to the physical layout of the device, and the circuits within the memory device that drive the internal clock, the internal clock signal is delayed with respect to the system clock signal. Consequently, the activation of the I/O circuits will be correspondingly delayed with respect to the system clock signal. Thus, while other synchronous devices will be expecting a data access according to the system clock, actual data access is delayed with respect to the system clock.
One way to overcome propagation delay in an internal clock, is to maintain the internal clock at the system clock frequency, but phase shift the internal clock forward. Using the example described above, the semiconductor device would receive the system clock and phase shift it forward. Thus, the I/O circuits would be activated in nearly exact synchronism with the system clock, and data accesses would be possible as expected. The phase shifting of an internal clock can be accomplished with a phase locked loop (PLL) type circuit or a delay locked loop (DLL) type circuit. A PLL would shift an internal clock signal according to the phase difference between it and the system clock. A DLL delays the system clock to such an extent, that the resulting internal clock is effectively shifted forward in time.
Referring now to FIG. 1A a timing diagram is set forth illustrating an external system clock (shown as CLKX) and a phase shifted internal clock (shown as CLKI). Both clocks have the same period duration, shown as "T1." The CLKI signal is shown to be shifted forward in time with respect to the CLKI signal by an amount "t1." The CLKI can be alternately conceptualized as being delayed in time by the amount "d1" so as to be effectively shifted forward by the amount "t1." It is recalled that the amount t1 is intended to compensate for propagation delay within the memory device. Therefore, internally, functions within the memory device are shifted forward according to the phase shift tl.
A drawback to many PLL and some DLL circuits is that they may require substantial analog circuits. For example, a PLL circuit usually includes a voltage or current controlled oscillator to generate a periodic signal based on a phase shift. Analog circuits may require custom fitting into the layout of a memory device, complicating the design and possibly resulting in wasted space on the device. In addition, analog circuits can be susceptible to noise, producing erroneous responses in noisy environments. A further drawback to analog phase shifting approaches is that such circuits may require a number of clock signals to "lock" into the desired phase shift amount. Thus, a given time period must be allowed following the application of the system clock for an optimal internal clock response.
A limitation of many DLL approaches arises from the fact that the amount by which the system clock is delayed (d1 in FIG. 1A), and hence the amount by which the internal clock is shifted forward (t1 in FIG. 1A), is a fixed portion of the overall system clock period (T1 in FIG. 1A). Such an approach can result in a memory device having a limited system clock frequency operating range. Because the synchronous device functions are optimized for a given phase shift (t1 for example), an increase in the clock period can result in an increase in the phase shift. The synchronous device operation will then lead the system clock. Conversely, if the clock period is decreased, the phase shift is likewise decreased, and the synchronous device operation will lag the system clock.
The variance in phase shift caused by DLL circuits employing shifts based on total clock period is best understood by comparing FIG. 1A with FIG. 1B. FIG. 1B is a timing diagram illustrating the system clock CLKX, but at a greater period than that of FIG. 1A. FIG. 1B also includes the resulting internal clock signal, CLKI, created by delaying the CLKX signal (or shifting it forward). It is assumed that the CLKI signal of both FIG. 1A and 1B are generated by delaying their respective system clocks by approximately seven eighths of the total clock period. The resulting phase shift forward is one eighth of the clock period. Because the overall period of the CLKX signal in FIG. 1B is greater than that of FIG. 1A, the amount of phase shift in the CLKI signal of FIG. 1B is greater than that of FIG. 1A (t2&gt;t1). This can be problematic if the device operation is optimized for a propagation delay of t1, but is operating at the clock frequency of FIG. 1B, as the phase shift will be greater than desired.
It would be desirable to generate a clock circuit for a synchronous device that provides an internal phase shifted clock that maintains the same phase shift despite variations in the system clock.